cystech electronics corp. spec. no. : c912j3 issued date : 2015.06.17 revised date : page no. : 1/ 9 MTE09N06J3 cystek product specification n-channel enhancement mode power mosfet MTE09N06J3 features ? low on resistance ? simple drive requirement ? low gate charge ? fast switching characteristic ? pb-free lead plating and halogen-free package symbol outline ordering information device package shipping MTE09N06J3-0-t3-g to-252 (pb-free lead plating and halogen-free package) 2500 pcs / tape& reel to-252(dpak) MTE09N06J3 g gate d drain s source bv dss 60v i d @v gs =10v, t c =25 c 50a r ds(on) @v gs =10v, i d =20a 7 m (typ) r ds(on) @v gs =7v, i d =20a 7.9 m (typ) g d s environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t3 : 2500 pcs / tape & reel, 13? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c912j3 issued date : 2015.06.17 revised date : page no. : 2/ 9 MTE09N06J3 cystek product specification absolute maximum ratings (t c =25c) parameter symbol limits unit drain-source voltage (note 1) v ds 60 gate-source voltage v gs 20 v continuous drain current @t c =25 c, v gs =10v(silicon limit) (note 1) 70 continuous drain current @t c =100 c, v gs =10v(silicon limit) (note 1) 50 continuous drain current @t c =25 c, v gs =10v(package limit) (note 1) i d 50 continuous drain current @t a =25 c, v gs =10v (note 2) 13 continuous drain current @t a =70 c, v gs =10v (note 2) i dsm 10 pulsed drain current @ v gs =10v (note 3) i dm 180 avalanche current (note 3) i as 45 a single pulse avalanche energy @ l=0.1mh, i d =45a, v dd =25v (note 2) e as 101 repetitive avalanche energy (note 3) e ar 10 mj t c =25 c (note 1) 75 t c =100 c (note 1) p d 37.5 t a =25 c (note 2) 2.5 power dissipation t a =70 c (note 2) p dsm 1.6 w operating junction and storage temperature tj, tstg -55~+175 c thermal data parameter symbol value unit thermal resistance, junction-to-case, max r jc 2 c/w thermal resistance, junction-to-ambient, max (note 2) r ja 50 c/w thermal resistance, junction-to-ambient, max (note 4) r ja 110 c/w note : 1 . the power dissipation p d is based on t j(max) =175 c, using junction-to-case thermal resistance, and is more useful in setting the upper di ssipation limit for cases where additional heatsinking is used. 2 . the value of r ja is measured with the device mounted on 1 in 2 fr-4 board with 2 oz. copper, in a still air environment with t a =25 c. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150 c. the value in any given application depends on the user?s specific board design. 3 . repetitive rating, pulse width limited by junction temperature t j(max) =175 c. ratings are based on low frequency and low duty cycles to keep initial t j =25 c. 4. when mounted on the minimum pa d size recommended (pcb mount), t 10s.
cystech electronics corp. spec. no. : c912j3 issued date : 2015.06.17 revised date : page no. : 3/ 9 MTE09N06J3 cystek product specification characteristics (tj=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 60 - - v v gs =0v, i d =250 a ? bv dss / ? tj - 0.06 - v/ c reference to 25 c, i d =250 a v gs(th) 2.0 - 4.0 v v ds = v gs , i d =250 a *g fs - 29 - s v ds =5v, i d =20a i gss - - 100 na v gs = 20v - - 1 v ds =60v, v gs =0v i dss - - 10 a v ds =48v, v gs =0v, tj=125 c - 7 8.8 v gs =10v, i d =20a *r ds(on) - 7.9 13.5 m v gs =7v, i d =20a dynamic *qg - 32 - *qgs - 7.5 - *qgd - 9.7 - nc v dd =30v, i d =20a,v gs =10v *t d(on) - 16 - *tr - 22.8 - *t d(off) - 39.4 - *t f - 15 - ns v dd =30v, i d =20a, v gs =10v, r g =3 ciss - 1500 - coss - 272 - crss - 140 - pf v gs =0v, v ds =30v, f=1mhz rg - 2.2 - f=1mhz source-drain diode *i s - - 50 a *v sd - 0.69 1 v i s =1a, v gs =0v *trr - 21 - ns *qrr - 18.5 - nc v gs =0v, i f =20a, di f /dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2% recommended soldering footprint
cystech electronics corp. spec. no. : c912j3 issued date : 2015.06.17 revised date : page no. : 4/ 9 MTE09N06J3 cystek product specification typical characteristics typical output characteristics 0 30 60 90 120 150 180 012345 v ds , drain-source voltage(v) i d , drain current (a) 10v,9v v gs =4.5v 5 v 5.5v 6v 7v 8v brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 1 10 100 1000 0.01 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =10v v gs =7v v gs =4.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 024681 i dr , reverse drain current(a) v sd , source-drain voltage(v) 0 tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 40 80 120 160 200 024681 0 drain-source on-state resistance vs junction tempearture 0 0.5 1 1.5 2 2.5 3 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =20a r ds( on) @tj=25c : 7m typ. v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =20a
cystech electronics corp. spec. no. : c912j3 issued date : 2015.06.17 revised date : page no. : 5/ 9 MTE09N06J3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 100 1000 10000 0.1 1 10 100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 i d , drain current(a) g fs , forward transfer admittance(s) ta=25c pulsed v ds =5v gate charge characteristics 0 2 4 6 8 10 0 102030405060 qg, total gate charge(nc) v gs , gate-source voltage(v) v ds =30v i d =20a maximum safe operating area 0.01 0.1 1 10 100 1000 0.1 1 10 100 1000 v ds , drain-source voltage(v) i d , drain current(a) t c =25c, tj=175c v gs =10v, r jc =2c/w single pulse dc 100ms r dson limited 1s 100 s 1ms 10ms maximum drain current vs case temperature 0 10 20 30 40 50 60 70 80 25 50 75 100 125 150 175 t c , case temperature(c) i d , maximum drain current(a) v gs =10v, r jc =2c/w silicon limit package limit
cystech electronics corp. spec. no. : c912j3 issued date : 2015.06.17 revised date : page no. : 6/ 9 MTE09N06J3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 30 60 90 120 150 180 0246810 v gs , gate-source voltage(v) i d , drain current(a) v ds =10v single pulse power rating, junction to case 0 300 600 900 1200 1500 1800 2100 2400 2700 3000 0.001 0.01 0.1 1 10 100 pulse width(s) power (w) t j(max) =175c t c =25c r jc =2c/w transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r jc (t)=r(t)*r jc 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *r jc (t) 4.r jc =2c/w
cystech electronics corp. spec. no. : c912j3 issued date : 2015.06.17 revised date : page no. : 7/ 9 MTE09N06J3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c912j3 issued date : 2015.06.17 revised date : page no. : 8/ 9 MTE09N06J3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak 10-30 seconds 20-40 seconds temperature(tp) ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. issued date : 2015.06.17 revised date : page no. : 9/ 9 spec. no. : c912j3 MTE09N06J3 cystek product specification to-252 dimension inches marking: device n ame date code e09 n06 1 2 3 4 style: pin 1.gate 2.drain 3.source 4.drain 3-lead to-252 plastic surface mount package cystek package code: j3 millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.087 0.094 2.200 2.400 e 0.086 0.094 2.186 2.386 a1 0.000 0.005 0.000 0.127 e1 0.172 0.188 4.372 4.772 b 0.039 0.048 0.990 1.210 h 0.163 ref 4.140 ref b 0.026 0.034 0.660 0.860 k 0.190 ref 4.830 ref b1 0.026 0.034 0.660 0.860 l 0.386 0.409 9.800 10.400 c 0.018 0.023 0.460 0.580 l1 0.114 ref 2.900 ref c1 0.018 0.023 0.460 0.580 l2 0.055 0.067 1.400 1.700 d 0.256 0.264 6.500 6.700 l3 0.024 0.039 0.600 1.000 d1 0.201 0.215 5.100 5.460 p 0.026 ref 0.650 ref e 0.236 0.244 6.000 6.200 v 0.211 ref 5.350 ref notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead : pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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